Forte Goes Hollywood, Sort Of

For years now, customers and evaluators of Forte Design Systems have been able to learn a lot about our Cynthesizer high-level synthesis (HLS) tool without cracking open a user guide or phoning an FAE. That’s because anyone who starts using Cynthesizer is given a user account to our online CynthKB knowledge base, where they can browse through hundreds of technical articles covering topics from basic usage to highly abstract interfaces. These articles are written in an approachable, breezy style, and most have downloadable examples. We’ve put a lot into them with the intent of making Cynthesizer more useful, accessible and easier to understand. And don’t take our word for it. New users tell us all the time that our online articles are some of the best they have seen in the industry.

The same is true about our training. Customers who want to get started using Cynthesizer usually are treated to an onsite two or three day training class given by a Forte technical specialist. There’s even a compact one-day version for people a little strapped for time. The training slides and lab exercises aren’t just little canned examples out of a textbook. Cynthesizer has been out there longer than any other SystemC HLS tool and seen hundreds of tapeouts, and we’ve put all that experience into our training. It’s real-world stuff.  Someone who completes a Forte training class gets exposure to SystemC datapath and control-oriented coding styles.  They see HLS architectural exploration techniques and quality-of-results improvement tips, and they learn a unified verification scheme that can be applied directly to the problems modern designers are facing. Just ask them.

But even with all the accolades, we’re looking to make the CynthKB and training even better, and that’s why we’re going Hollywood — well, if by Hollywood you mean we’re going to start appearing in moving pictures…

Throughout 2014, Forte will be undertaking an effort to transform the way we teach our users. Coming online this year will be an extensive library of video training playlists.  Topics will cover SystemC coding techniques, Cynthesizer usage, and turning your modules into fully verified architectures with optimal throughput and latency.  And there will be others covering things like memories, interfaces, hierarchy, datapath optimization and more.  Each major section of training will be presented as a video module, and the user will be able to watch as we go through each lab exercise step by step.

Webified training has advantages for any type of user. Instead of the hassles of onsite training (booking conference rooms, coordinating attendee schedules, travel, etc.), individual users can go to the Forte website and get trained at their own pace and on their own time.  And they have the freedom to pick and choose how they do it.  If a designer works mainly with complex line buffer interfaces, or their upcoming project has floating point arithmetic, they can watch those playlists and get right to what they need.

So look for these new ways to see and hear Forte.  We’re excited about bringing this to you, and welcome your feedback on how we can make learning Cynthesizer the best experience it can be.  Oh, and if you haven’t had a chance to see or use the CynthKB knowledge base, contact your Forte Design Systems representative for a user account and check it out.  It’s just a click away at

Plenty To See On The Forte YouTube Channel

Yes, Forte Design Systems has a YouTube™ Channel. We could have announced it when it went online months ago, but we wanted to wait until it had a lot of videos and a good variety of high level design topics before we made a big deal about it.  And now, with 40 videos, 121 subscribers and over 10000 total views, it is a big deal.

Forte YouTube Channel Main Page

Located at, the channel starts with a short introductory statement from Forte Design Systems CEO Sean Dart.  In it he pretty much spells out the whole reason the channel exists: education.  The videos are organized with the intent of “educating you on various issues related to high level synthesis in general and Cynthesizer in particular.”

Below his introduction are groups of video playlists.  The first playlist has three videos that lay out and define the space that Forte plays in: high level synthesis.  Here you’ll find out what high level synthesis is and learn about some of its basic terminology like scheduling and latency.  And if you’re a Verilog coder, someone who has never written anything but register transfers in your life, there’s a video that takes you by the hand and walks you through how to write a multicycle algorithm.

The next playlist serves as a primer on Cynthesizer, Forte’s flagship product.  It introduces the Cynthesizer Workbench GUI and its new SystemC IDE interface, and devotes individual videos to the GUI elements of editing, debugging and analysis.  Then it finishes with a “top 10” shortcuts video showing you all the handy keystrokes, mouse scrolls, GUI button equivalents and pane arrangments that you’ll definitely get in the habit of using.

Following that is one of our most watched playlists, Learn SystemC.  This is a progression of six videos that introduce the SystemC class libraries, and show you how to write modules with solid threads for synthesis and verification, everything you’ll need to know right up to the point of using Cynthesizer.

The last three playlists have actual product demos that take you through the application of Cynthesizer in simple point-to-point designs and a complex edge detection filter that uses very abstract line buffer interfaces.  There’s also a video of Forte’s Mike Meredith giving his Why SystemC? lecture at DVCon.  And what better way to finish than with a few videos of a popular DAC tradition from past years: the closing bagpipers at the Forte Design Systems booth.

The most recent addition to our channel?  Japanese language translations.  In the last few weeks Japanese translations of the Introduction to CynthWB and Learn SystemC playlists have been added, with Kanji fonts and everything.

Even without much promotion, a lot of people out there have discovered the Forte YouTube Channel.  Several of the videos have been watched well over a thousand times, and a few of those viewers have voluntarily posted some very nice compliments.  Out of respect for their privacy I don’t want to quote any of them directly here, but the general sentiment is that the videos are easy to learn, logically presented, and much appreciated.  And many of them end the same way: keep the videos coming.

And that’s exactly what we intend to do.  In 2014 you will see more and more videos posted.  They will add more content to the current playlists, and get into other areas we want to cover like interfaces and designing for lower power.  And like Sean says in his video introduction, “we welcome your feedback.”  Go to, watch our videos, and join the other posters by letting us know what you think and what else you want to see.

Will History Repeat Itself?

In a recent issue of Semiconductor Engineering, technology editor Brian Bailey dredges up some of the early attempts the EDA industry made at high-level synthesis. While he correctly points out that the designs from that era (mid-1990s) were cycle-accurate and the languages used were not suited to the task, things have changed for the better. Speaking to many people who have been with HLS since the start (including Forte’s own Brett Cline), Bailey poses the question of where HLS has been, where it’s going, and how it fits with what you are doing now. We think you’ll like the answers he gets. Enjoy, Kirk.

EDA Tool Chain Too Complex

We wanted to share with you an October 22 article that appeared in EE Times.  In it, editor-in-chief Brian Fuller interviews our CTO John Sanguinetti, who observes that EDA startups have a harder time getting in the game today because of the complexities of tool flows.   Here’s the link below.  Enjoy!  Kirk.

Forte and Cadence at DAC: How to Deploy High-Level Synthesis

It’s no secret that the transition to high-level synthesis (HLS) has historically gone more slowly than expected. There were a number of reasons for this – the early tools could not successfully synthesize control logic, they could not match the quality of results of handwritten RTL, and there was no standard input language or subset that could be used to build a full design and verification methodology. These issues have been resolved with the introduction of the latest generation of HLS tools.

At Cadence and Forte we have been working with major customers throughout the world to transition their production methodologies from RTL-driven design and verification up to SystemC-driven design and verification. As expected, a lot of this happened first in Japan, but recent years has seen rapid expansion into the other regions, especially Asia-Pacific and some of the major North America-based semiconductor companies.

While we are competitors, we agree on more than we disagree on. We agree that there are huge productivity gains to be had by moving up the abstraction level of design and verification, as well as benefits of broader micro-architecture exploration and easier re-use. We agree that SystemC is the best language for this abstraction level because it is built on C/C++ but adds hardware-specific constructs. We agree about the profile and skill set required to adopt this methodology. We agree that in order to make this transition, it must augment existing methodologies. And we agree on the best way to transition to and proliferate this new methodology extension within a company. Of course one of our major disagreements is who has the better HLS tool.

We have read and heard about so many reports of new IP design requiring armies of engineers and months or years to complete, causing outsourcing of new IP development. Meanwhile we have been working with customers — especially customers with no legacy methodology to hold them back — adopt this high-level approach and complete large and complex designs in a fraction of the time with comparable or better QoR. So we thought that it would be useful to share our experiences — at least on those areas where we agree – with the DAC audience.

This is an audio recording of our DAC 2013 Cadence Theater presentation with slides. Mike Meredith and Mark Warren each lead our field deployment efforts and do an excellent job of concisely summarizing these topics while lending their unique perspectives. Hopefully you find this useful and we can discuss in more detail in follow-up meetings.

Brett Cline, Forte Design Systems

Jack Erickson, Cadence Design Systems

Mike In India

When designers gathered in Noida, India for the annual India SystemC User’s Group (ISCUG) Conference recently, Forte’s Mike Meredith was there. As our Vice President of Technical Marketing and former president of the Open SystemC Initiative (OSCI), Mike is well known in the SystemC community. He was there to present to a large and enthusiastic group of designers, a designer community ready to embrace a SystemC-based chip design approach with many already having adopted high-level synthesis (HLS).

Mike Meredith

Forte's Mike Meredith

Starting with a three-hour tutorial titled “Using SystemC for high-level synthesis and integration with TLM (transaction-level modeling),” Mike covered the key reasons for raising the abstraction level and looked at the synthesizable SystemC subset that makes HLS a practical reality. Mike talked about the history and “basics” of HLS, provided an in-depth analysis of what HLS is, and dove into the intricacies of HLS and SystemC that he is so uniquely qualified to cover. He concluded the presentation with user experiences, and later on gave an additional talk called “A look at the origins of SystemC and the future directions of SystemC”.  His entire presentation is available on our website.

ISCUG was a big success for Forte Design Systems, and we want to thank Umesh Susodia of CircuitSutra for organizing this great event.  Take a look at the event photos (where Mike isn’t too hard to spot).

In the end, Mike obviously generated a lot of interest in HLS — he spent the rest of the week demonstrating Cynthesizer onsite at companies all over India.

If you couldn’t make it to ISCUG and want to see what all the fuss is about, there’s a great opportunity coming up — DAC! Come on down to Austin June 2-6 and see us in booth #1547, where you can register for one of our sessions and see for yourself.

Happy Cynthesizing!


The Man Who Came Back to HLS: Observations of a Reformed FAE

I’m coming back into the field of High Level Synthesis after a sojourn in emulation, and I’m struck by the parallels between the two industries. Eight years ago, most chip companies were not interested in using emulation. The majority of engineers didn’t have any direct experience with emulation, but they had heard it was expensive and hard to use. The engineers that did have some experience with it often had a bad experience, and didn’t want to try it again. The management wasn’t interested in looking at emulation because their current methodology had worked fine for their last chip. The combination of ignorance and complacence made it easy for these companies to dismiss emulation as unnecessary.

There were a few companies getting a lot of value from emulation, but they were being very quiet about it. These folks saw emulation as a competitive advantage and they didn’t want to let their competition know what they were doing. They were right (selfish, but right), and their refusal to talk about what they were doing reinforced the prevailing opinion that emulation wasn’t interesting .

The increasing demand for modeling complex software running on complex hardware before the hardware design is committed to silicon put enormous pressure on software simulation systems, and changed emulation from a competitive advantage into a competitive necessity for many types of SoC designs. Companies that didn’t want to think about emulation before are now scrambling to adopt it–a really painful process when you have to simultaneously figure out how to use it, and get it working on your production project.

So how does this compare with the High Level Synthesis market? The HLS market is almost identical to the emulation market 10 years ago. There are a number of designers that have been using HLS for production designs for years, but they don’t want anybody to know about it. Most of the engineering community has a vague notion that HLS is difficult to use and not very effective, completely unaware of what a modern HLS tool can do. The engineers who have experience with first generation HLS tools don’t want to try HLS again. Management sees that the existing RTL methodology worked for the last chip, and therefore thinks there is no pressure to change. But the pressure is there. There is demand for the ability to produce more high quality RTL faster. There is demand for efficient design reuse. There is demand for the ability to rapidly change implementation technology. HLS satisfies all of these demands. It’s hard to predict when one of these demands will become critical for your business, but when it does (and it is when, not if), the history of emulation shows that the people who were thinking ahead have a much happier life.

Forte has been delivering HLS since the early 2000’s and the technology goes back even further than that. When I worked on HLS in the mid-2000’s, adoption was primarily limited to a bunch of forward thinking Japanese companies and a handful of others around the world. Things have changed in the last 8 years. Now, some of the largest and most successful US companies have invested heavily as well as leaders in Korea, Taiwan, India, and other major regions.

If you evaluated HLS tools a long time ago and thought they just weren’t ready, it may be time to take another look.  I just took another look myself, and I rejoined Forte Design Systems because of it.  I’m now in a position to help companies that are interested in HLS jump in and achieve first time success. It reminds me a lot of when I joined the emulation field 8 years ago and the road to success seemed impassable. With a truly mature HLS tool like Forte Cynthesizer, there are bridges, shortcuts and fast lanes you never knew existed.

2012: A Banner Year for Cynthesizer … Thanks to You!

Hello, everyone,

Thank you for helping make 2012 a banner year for Cynthesizer High-Level Synthesis. Cynthesizer now has more than 1,400 registered users and has had incredible growth in the USA, Korea, and Japan. Cynthesizer was also named the #1 high-level synthesis product by Gary Smith of Gary Smith EDA in his 2011 market share report.

Last week, we announced that Hitachi JTE became a customer in late 2012, joining other large customers in Taiwan, Japan, Korea, and the USA. We expect this trend to continue as design teams move away from other HLS tools limited to ANSI-C and block-based design. Many of you have told us what we’ve been saying all these years is true: it may be easy to start a design with these other tools, but to get your design out the door you need the high-level approach of SystemC and Cynthesizer.

While 2012 was a great year for Forte, we aren’t standing still. Our product team is hard at work developing a number of new features and capabilities designed to get you better results in less time. We’ve announced support for SystemC 2.3 and that is just the tip of the iceberg. We’ll have more features, SystemC IP, and new products rolling out soon. Stay tuned for more news from us over the coming months.

The team will also be out and about throughout the year at major conferences and trade shows, including DVCon, DATE, SNUG DCE, SystemC India, SystemC Japan, and DAC.  Don’t forget to come by and see why each year more of you are choosing Cynthesizer SystemC synthesis for your leading-edge ASIC, SoC, and FPGA designs.

Thanks again to all of you for continuing to make Cynthesizer the industry standard for high-level synthesis.  We look forward to making you even more successful in 2013!


A Forte Design Systems Profile From EDACafe

Russ Henke, a contributing editor at EDACafe, recently profiled Forte. We’re repurposing it here in its entirety because we think it’s an accurate depiction of where we’ve come from and what we’ve accomplished.

We hope you like it as much as we do. Please send your comments.

A Profile of Forte Design Systems

Let’s start with a picture of a building that’s likely to appear familiar to a lot of readers – the front of the New York City Public Library.

New York City Public Library

Did you know that the two marble lions prominently visible in front of the famous library are named “Patience” and “Fortitude?” We shall see how these words might also describe many of the people of Forte Design Systems, and perhaps similarly named statues should be placed in front of Forte’s headquarters at 100 Century Center Court in San Jose, CA.

Forte Design Systems logo

The tale of this high-level synthesis company starts with the successful 2001 merger of two companies, CynApps and Chronology. Executives of the newly formed company wisely chose a descriptive name for the combined company, since “forte” means “good at” or “strength” though patience and fortitude, and the people of Forte have both in abundance.

Brett Cline

Forte’s long-time vice president of marketing and sales Brett Cline said the following: “Forte’s been around for many years now and is the major driver of a whole new market segment. I consider us to be a definer of the high-level synthesis market. And, we’re good at it.”

The Forte Corporate Culture and its Founder
Let’s pause here and define from 10,000 feet the term “high-level synthesis software.” From all accounts, it enables electronics hardware engineers to work at a higher level of design abstraction.

Any story about Forte must start with Dr. John Sanguinetti, the EDA luminary noted for launching Chronologic in the 1990s and developing VCS, the Verilog Compiled Simulator, which is still in widespread use today.

After Chronologic was acquired by Viewlogic in 1994, he started looking for his next adventure. (As an aside, Viewlogic was itself acquired by Synopsys in 1997). Since Dr. Sanguinetti’s expertise was performance analysis and design verification, he understood that there were two basic problem areas in EDA –– logic verification and logic synthesis. He already had tackled logic verification; a closer look at logic synthesis seemed in order. For more than a decade, he had known that a change in abstraction levels from gates to RTL (Register Transfer Level –> see ”Acronyms” at conclusion of article) would improve design and verification efficiency, and that such a change might be enabled by logic synthesis.

Dr. John Sanguinetti

A true entrepreneur in every sense of the word, John is Forte’s CTO today. He is also a 2011 ACM Fellow for contributions to hardware simulation. He serves as a role model and mentor for many entrepreneurs and engineers and has been quoted as saying: “In a technical field like EDA, understanding the problem, and understanding the technology, are prerequisites.”

Since John’s name is synonymous with the word entrepreneur, let’s find out how that came to pass. “I was caught up in startup fever from my first year in the Valley (1982). Ardent was my first real startup (1986), but it was a big-time operation –– I was #24. After that, I knew I wanted to start something, but it took a while to figure out what.” That something was Chronologic.

John has been and continues as an active angel investor in the EDA industry, helping drive EDA technology and businesses forward. He has put “seed” funding into many EDA companies that have had successful exits, including Ambit, Magma, Moscape, CoDesign, Surefire, Hier Design, Innologic and, most recently, Nextop. John has been or is actively involved in more than 20 other ventures as an angel investor, mostly in EDA and many still going.

Becoming an angel investor started innocently enough. “I was introduced to Rajeev Madhavan right after selling Chronologic to Viewlogic. Rajeev was trying to start Ambit, and I was interested right away.”

Rajeev Madhavan

“I spent lots of time with Rajeev trying to pitch Ambit to interested VC’s. I not only made money on the investment, but gained a good friend, and felt like I had made a contribution to a worthwhile venture.”

John said he had no investment formula when he got started and referred to his early choices as “haphazard.” Many entrepreneurs approached him after his success with Chronologic and he found it hard to say no. After five or six years and a string of failures of promising ideas and technology in divergent fields, John restricted himself to EDA. “So far, none of my non-EDA investments had a positive return. All of my successes have been EDA.”

Influence on Forte
John’s technical vision, business acumen and hard-earned experience are strong parts of the corporate culture at Forte Design Systems.

Telecommuting has long been another hallmark of Forte’s corporate culture, something that’s far more common today with other companies than it was in 2001. Forte may be headquartered in San Jose, but it also has offices throughout the United States, including Pittsburgh PA, and Redmond WA, and international offices in England, Japan and Korea.

As Brett Cline, who works from Boston, pointed out, “It’s a small world. We may be in different states or on different continents, but we make use of all the available collaboration tools.” And it seems to be working.

The Forte team at the 49th DAC, San Francisco, June 2012

Carving Out the High-Level Synthesis Market
In 1998, John Sanguinetti and two other engineers founded CynApps to create a higher level design environment, along with a synthesis product that would produce RTL code from higher level designs. A tool challenge and one not easily solved, and it took a long, long time, but Forte finally did it.

In this achievement we realize that this is where patience and fortitude paid off. Forte succeeded where other companies haven’t, by exhibiting dogged determination, winning over design teams one at a time, while the industry as a whole struggled to define the market category.

Long-time EDACafe readers might well recall the names of other companies with behavioral synthesis that morphed into architectural synthesis, ESL and algorithmic synthesis. None of the names stuck and their tools eventually failed. But Forte stayed on course with high-level synthesis, a term now widely adopted by the EDA industry, as the production-quality tools themselves go mainstream.

Success has finally come to Forte. John gives loads of credit to investors who believed in Forte and didn’t give up. In particular, Sam Lee, managing director at Infinity Capital, has been an investor since December 1999 and holds a board seat. Likewise, another EDA luminary Lucio Lanza of Lanza TechVentures participated in Forte’s Series A funding way back in November 1998 and has served continuously as chairman of the Forte board. “Stalwart” is the word John uses to describe both.

As an aside, investors in Forte’s first round of funding reads like a Silicon Valley Who’s Who: Andy Bechtolsheim, who was that series’ largest investor; Gordon Bell; Steve Blank; Paul Huang; and Jon Rubinstein.

Meet Sean Dart of Forte
Sean Dart is Forte’s CEO and is highly technical, an unusual combination in today’s business climate, but vital to an emerging EDA company. Sean grew up in a small town 400 miles north of Sydney, Australia, and moved to Sydney to study computer science at New South Wales University.

Forte CEO Sean Dart

His decision to study computers was a curious one, considering Sean had never seen a computer. The decision came after talking to career counselors. He was a good student in all subjects but preferred scientific studies. The advice he received was that computing was the up and coming field. This appealed to Sean because he could combine his interest in math with the practical, giving him an opportunity to merge the intellectual with a job. And, he loved it.

Today, everybody has a personal computer, so it’s difficult to imagine the days of computer centers. [Maybe for Nanette, but not for others, such as your Contributing Editor]. Sean said that he and his colleagues used hand-marked cards, not even key punched cards. He mused that even later, the 30 VAX terminals from the computer lab at his college had one-thousandth the capabilities of an iPhone.

Sean’s first job out of college was working for STC (Standards Telephones & Cables) in Australia designing embedded programming for PBX systems. After two years, he was designing operating systems for small business computers and then moved on to Olivetti. He was subsequently transferred to Colorado to work with AT&T to customize telecommunications equipment for the Australian market. Once that project was abandoned, Sean and his American wife moved to Switzerland where he worked for a company that second-sourced ASIC designs. His role was to manage the network and develop tools and utilities to support the design services team. The company needed utilities, especially for verification, to help retarget designs.

After a fashion, the company decided it was making more money in the tools area and became an ESDA company, Sean’s introduction into EDA and a forerunner to high-level synthesis. The company, Speed Electronics, was sold in 1997 to Mentor Graphics.

After 10 years in Switzerland, the Dart family, that now included two children, relocated to Silicon Valley in pre-Internet 1997 but quickly discovered that the SF Bay Area was an expensive place to raise a family. After looking around the EDA companies in the Seattle and Boston areas, he liked what he saw at Chronology in Redmond, Wash., less than 20 miles from Seattle.

So in 1997, after only five months in Silicon Valley, he and his family moved to a town 15 miles east of Redmond. “It’s a great place to live,” he noted.

It’s at this point that we need to hear more from Brett Cline, who truly has his finger on the pulse of the high-level synthesis market and someone who has been a major contributor to Forte’s success. Brett may be a bit more informal than the consummate executive of old, but one is not fooled by the informality. Anyone who talks to him will pick up on his competitive streak. “Massively competitive,” he admitted, “I hate to lose and don’t accept losses that well. I push myself to do things better and I try to encourage others to exceed as well.” He admires winners, but firmly believes that it’s important to be a team player as well, something that’s apparently important as well to the 35 or so Forte employees.

You may have also heard that Brett is one marketing executive willing to dress in costume, as the situation calls for it. In 2003, he donned a hockey goalie uniform to present a DVCon paper titled, “Why You or Your Replacement will Use SystemC for System Design,” claiming he needed the padding for his defense in front of a room of skeptical RTL designers.

In 2005, Brett dressed in a chicken suit at DAC after losing a bet to John Cooley, editor of ESNUG and DeepChip. They agreed to a “Gentlemen’s Bet” over whether SystemC adoption would be more than 50% in the results of the DeepChip Verification Census. Brett said it would, John Cooley said it wouldn’t. John Cooley ruled that day, “but he was counting the votes,” laughed Brett. “It would be interesting to see if he is willing to make that bet again now.”

Brett in the chicken suit

© 2012 Forte Design Systems/Brett Cline

Brett still in the chicken suit talking with John Cooley

© 2012 Forte Design Systems / Brett Cline

Brett is a friendly New Englander who grew up in Manchester, CT. He moved to Boston to attend Northeastern University and worked at GE as a co-op student. EDA has a few Northeastern grads, but younger readers may not know that Northeastern is renowned for its five-year co-op program where students get real-world experience by working in companies before graduating (Other schools of course offer co-op university programs, such as the University of Cincinnati where the Contributing Editor obtained his engineering degrees).

After graduating, Cadence in Massachusetts came calling because Brett’s background included both hardware and software. Brett was put to work on a waveform project, then VHDL simulation graphical tools and was tasked to work with the SimVision team. He enjoyed working with the sales and FAEs, and eventually moved into technical marketing for many of the same products he had spent time building.

SimTech recruited him in 1997 to be the East Coast application engineer, before SimTech was acquired by Summit Design that same year. In 1998, he ran marketing for the ex-SimTech products, then picked up corporate communications responsibilities as well.

It was in November 1999 that Brett called a friend at CynApps about joining. He knew the legend of Dr. John Sanguinetti from late nights at Cadence working with the Verilog-XL and NC-Sim teams to compete with VCS and Brett was eager to meet Dr. Sanguinetti.

Brett liked much of the CynApps story, especially the verification piece, but he remained a bit skeptical about behavioral synthesis, a still unproven technology. He wasn’t certain the electronics industry was ready for behavioral synthesis, but he became more and more excited about CynApps’ entire product portfolio, including a simulation library that could be marketed as an open source product with C++ simulation, services and debug and analysis tools that captured his imagination. He signed on and then CynApps acquired DASYS in January 2000, which further cemented the focus on behavioral synthesis.

Concluding remarks about John Sanguinetti
The first thing one learns about John Sanguinetti when talking with him, is his modesty. The second is his candor.

When asked what influenced him to study computer science, John said, “After my freshman year of college, I had a summer job in the Navy Department in Washington, D.C. where I wrote output reports in Fortran for a shipyard simulation program that was being developed. I learned Fortran from a self-study course that the government had. After that, I took as many programming courses as I could. This was 1967-70, when Computer Science was not much more than programming courses.”

While many of us associate John with Michigan and the University of Michigan, he’s originally from Silver Spring, MD, a suburb of Washington, D.C. “I went to college at University of Michigan for 11 years, so it’s fair to say I’m from Michigan, too.”

His fondness of the University of Michigan and Ann Arbor is strong. He met his wife in college and his daughter Anne was born in Michigan. “I still go back there to play in the alumni Marching Band at homecoming,” noted John. A fine trombone player since he was a teenager, he has also performed with the Peninsula Symphony for 25 years.

We talked as he was getting ready to leave on a vacation at the Maryland home he owns, a home that has been in his family for many years. It sits on the beach of the Chesapeake Bay, giving him ample opportunity to sail his Sunfish sailboat off the beach or take the wooden kayak he and his wife built several years ago.

Yes, a wooden kayak. John recalled finding a company that sells kits for building wooden boats. Over the course of two summers, two weeks at a time, they built a kayak now housed at Chesapeake Bay. He said, with characteristic modesty, that the experience was like any other woodworking project, which meant following directions. It was straightforward, though he recalled lots of sanding. And definitely a bit of patience and fortitude.

The wooden kayak

Merging Chronology and CynApps
The 2001 merger of CynApps and Chronology created an interesting dilemma and one that was debated all the way to the board room. The question was how to make Forte Design Systems both a verification company and a synthesis company. Chronology was making money as a verification provider, but was not doing as well as Verisity (now part of Cadence).

CynApps was making a little money in the synthesis area, though not enough to pay all the bills; however, it was able to secure funding to grow the company. The decision was made to continue to focus on high-level synthesis and to utilize the plethora of verification tools to build a high-level synthesis environment with verification at its core.

And in that same year, Sony, Ricoh and Fujitsu became high-level synthesis customers of the newly combined Forte and the push was on.

Moving to a high-level synthesis business model was practical. Cynthesizer, Forte’s high-level synthesis software, was gaining traction, though Brett Cline said that the first few years of the merger were killers as Forte honed down at least five products into essentially just one with add-on capabilities. (Chronology’s TimingDesigner was still around in a separate division and ultimately sold to EMA Design Automation in 2007.)

Asia adopted a high-level synthesis methodology ahead of other world regions, willingly making a huge investment in a methodology shift. John, Sean and Brett all credit this turning point to the large number of consumer electronics companies. The high-level synthesis trend started in Japan because consumer device designs were a natural fit for this kind of software. High-level synthesis can implement image-manipulation algorithms, for example, into hardware. Japanese hardware engineers saw high-level synthesis as a way to stay ahead of the design curve from challengers in Korea and China. Moving up the abstraction level and adopting SystemC was a way to leapfrog ahead.

Brett acknowledged a few key and savvy individuals who led this methodology shift, many of whom are still in the business.

At this point in our interview, Brett opened up a spreadsheet and noted that Japan accounted for 99% of 2004 HLS revenue. Over time, it’s become about half of Forte’s revenue and still remains a large and important region.  United States, Korea and Japan, in particular, are design centers where Cynthesizer is in use for all kinds of applications. The USA is Forte’s fastest growing region, designing everything from custom processors to wired and wireless communication devices.

As we’ve seen in this profile, acquisitions have been good for Forte and it did another in 2009. It acquired Arithmatica to complement its product offerings with a portfolio of IP and datapath synthesis technology that has been integrated directly into Forte’s Cynthesizer product.

Typical Cynthesizer design flow

Today, Cynthesizer is chosen primarily by design teams that want to reduce time-to-market pressures by designing at a higher level of abstraction and who require substantial improvements in circuit size and power. In many cases, teams create designs that would be impossible using RTL with their given resources.

The long-term benefit is generally not well understood. The value of SystemC-based IP and the ease at which it can be retargeted and reused is at the beginning of a project, are some things Verilog RTL has never achieved.

A Long Trek for Forte
“It’s been a long trek, in terms of finding the right set of customers who need a flexible format for IP reuse for the future,” said CEO Sean Dart. “Getting a product to that point was much harder than we expected. In 2000-2001, we never expected it to be this difficult. People shrug their shoulders and say, what’s so hard about a translator with clock cycles, far under-estimating what’s involved. The high-level synthesis tool needs to be able to handle different kinds of design styles, implementation methods and coding styles. It must be able to work with all of the downstream tools and libraries. It’s hundreds of things. Everybody underestimates the project.”

Many designers still hand code RTL for most of their designs, even now. Sean noted there’s a bit of inertia in the designer world, and Brett agreed. After all, any new change in the design flow can create more problems. For a designer, it introduces something new –– risk. They need to write in another language at another level of abstraction and change from what has been comfortable for them. “For a company like Forte, we need to prove we can make people successful and show a flexible format for reusing IP where a designer can get great results,” remarked Sean.

And, it finally happened with Cynthesizer. “We created a groundswell of support,” Sean stated, with Brett nodding his head in agreement. “Designers came to understand the utility. Otherwise, their product will miss the time-to-market window. IP development is so much shorter. Once people have the experience, then a second experience, that’s when the groundswell happened.”

He continued: “IP must be compatible and it should be automatically implementable. It’s a key selling point for us. There are reasons to buy the first time and a reason for change. Design teams don’t go into high-level synthesis for IP that will give them two or three times performance. However, as process geometries get smaller, fully timed RTL IP may not be reusable. That’s where high-level synthesis can make a difference.”

At this point, Sean became even more animated and noted: “High-level synthesis offers a way for designs to be retargetable for the next level and an optimal solution for technology, speed and longevity of the design. A key selling point for Cynthesizer is that the IP can be used on another project with almost zero effort.” Forte estimates that while the productivity gain on first development of an HLS-based IP may be 5-10X, reusing that IP block next time around yields over 25X.

“Design teams are experiencing that reuse benefit,” he concluded.

The Career Opportunity
A small company like Forte can offer loads of opportunity, as Sean and Brett found.

Sean’s moved into the CEO position in 2006 and yet is completely comfortable talking with engineering teams and understands their technical challenges. He can see their point of view and feel the pain of their daily lives.

Meeting customers, setting product directions was something Sean did as vice president of engineering. He was involved in many high-level meetings and traveled to Asia quite often. When he moved into the role of CEO, he learned more about the financial side of the business and working with the board and investors. Since assuming the CEO role, he sold a division (Chronology’s Timing Designer in 2007) and acquired a company (Arithmatica in 2009).

“I’ve had three different jobs at Forte and watched about 30 competitors come and go,” affirmed Brett. He started out in marketing at CynApps and was sidetracked in 2005 to work in an operations role for Forte. His task was to set up a post-sales support organization to make sure that Forte serviced its customers to ensure their success. That meant an explicit focus in post-sales support rather than an implicit one. “I’ve always tried to dive into whatever needed to be done and deliver to the best of my ability and, at the time, this was extremely important,” he reported. “Small companies must work closely with every customer to make sure each design project is a success.”

With that mission accomplished, Brett went back to marketing and took over sales in 2006. “We have grown each year since 2006 and we are proud of it,” he said. He also takes pride in having done a lot of things to merge new companies into Forte.

At this point, John Sanguinetti interjected: “It’s gotten a lot easier than it was before. I take a step back and see the market coming around to understand the need for high-level synthesis.” From there, he described a more mature product and a codified sales process that helps identify and better qualify opportunities, something Brett’s done over the past four years.

Sean concurred. Forte’s doing well and, from his perspective, keeping the momentum going is all important. His goal and one shared by Brett and John is to keep the team executing. “Our charter should be to create relationships with customers to get paid fairly for our products. The real trick is to deliver enough value and to be paid fairly for what we do.”

The EDA Industry
As the interview came to a close, Sean was asked for his perspective on EDA. He paused for a moment and answered: “Often the goals of the large (EDA) companies are different from those of the small (EDA) companies. Disrupting the status quo isn’t such a bad thing,” he added and believes that the need for continued innovation comes from small companies. “EDA is a small industry, but an important one. What would happen if everyone in EDA quit to build web pages? It would stop the world economy. We do have an important place in the ecosystem and should be recognized. We need to foster small EDA companies.”

John Sanguinetti, of course, agreed and had one final comment about Forte: “Patience and fortitude really do characterize Forte. We’ve kept at it and appreciate our success.”

So ends our current profile of Forte Design Systems. If personalities are the foundation of a successful company, Forte has them in spades. Forte’s people clearly exhibit the qualities from the names of the two lions in front of the New York Public Library: Patience and Fortitude!

Note: Forte has been the sponsor of a live bagpipers’ performance at DAC since 2001. EDACafe’s Peggy Aycinena captured this year’s performance. Her video is posted on her blog, “49DAC Unplugged:

ACM: Association for Computing Machinery
CEO: Chief Executive Officer
CTO: Chief Technical Officer
DAC: Design Automation Conference
EDA: Electronic Design Automation
ESDA: Electronic Systems Design Automation
ESL: Electronic System Level
GE: General Electric
nm: Nanometer
I/O: Input/Output
IP: Intellectual Property
RTL: Register Transfer Level
SoC: System on Chip
STC: Standards Telephones & Cables
VAX: Virtual Address eXtension, an early mainframe computer from Digital Equipment Corporation (DEC)
VCs: Venture Capitalists
VCS: Verilog Compiled Simulator

Forte Coverage:

EDN: “Sage words of advice from Forte Design Systems founder John Sanguinetti” by Brian Bailey

EDN: “Time to rethink EDA flows and tool infrastructure” by Brian Bailey

EDACafe’s What Would Joe Do: Forte: “Anchor Tenant in the ESL Mall” by Peggy Aycinena

EETimes: “2012 will be the year of power, again” by Brett Cline

EETimes’ EDA DesignLine: “Control dominated design” by Mike Meredith

EETimes’ EDA DesignLine: “Gearing Up for DAC – Above RTL” by Brian Bailey

Electronic Design: “Implement Abstraction By Encapsulation In SystemC” by Mike Meredith and John Sanguinetti

GABEonEDA: “Bagpipers a DAC Tradition” by Brett Cline

High-level Synthesis is not just for Hardware Designers, It’s for Verification Engineers, too!

We’ve seen an uptick in interest in high-level synthesis (HLS) around the world lately. Some of the increased interest is from designers that have MBOs to investigate HLS in 2012. Some interest is from the visibility that Forte’s Cynthesizer and HLS have had this year. And some is from people that simply do not have enough time to get their projects done with the allocated resources. This is where we can really help.

Cynthesizer automates many of the mundane coding tasks that hardware designers have to suffer with using Verilog daily. Through that automation, it will allow designers to quickly perform “what if analysis” on their macro and micro-architectural decisions without wasting months of effort.

Since the design model will now be in SystemC, a C++ class library, the functional code will be written in C or C++. Technically, it’s all C++ because we are using a C++ compiler, but the reality is that ANSI-C can pretty much be used as-is. The benefit of SystemC and C++ come from the addition of hierarchy, clock and bit accuracy, and other hardware specifics not available in standard ANSI-C. And, since SystemC is an IEEE standard, designers know that they are being locked into a proprietary language or set of extensions.

We are often asked about the verification benefits of using SystemC models for design and it’s a great question. While there are numerous others, here are three areas that will benefit from the higher-level approach.

First, hardware design and verification teams will benefit from significantly higher performance models. SystemC models typically run between 10x and 100x faster than RTL Verilog and even faster in some cases. This allows verification teams to setup and debug their verification environment faster, as well as run far more cycles through the high-level model. Since the model can be either a transaction-level model (TLM) or a pin-cycle accurate model (PCA), the verification team can vary the level of interface detail while maintaining high-level functional code.

Second, this model can be used for Virtual System Prototypes (VSPs). These highly abstracted models require far less code to implement (usually 10-20x less code) and are available months before the RTL designs.

Third, the SystemC model with HLS can be quickly targeted for an acceleration or emulation platform, including some of the big emulator “boxes” as well has home-grown FPGA solutions. This flow gives design and verification teams the best of both worlds –– the ability to quickly make changes, and get results into the hardware and get hardware accurate simulations at high speeds. Since SystemC models for Cynthesizer are technology independent, they can be quickly retargeted from FPGA to ASIC and back saving time.

Obviously, some of these benefits are hard to quantify. If we simply look at hardware verification benefits, we can quantify some. Working with a design team, we collected data using an ARM bus-based multi-function printer system. The design consisted of several blocks, both control and datapath, entirely in SystemC.

Here’s a look at simulation performance and the huge difference between the TLM behavioral model and the Verilog RTL model –– almost 500x!:

* This is a process by which the Cynthesizer RTL output is converted to cycle accurate SystemC and simulated in SystemC.

We also measured lines of code for each design:

While generated code tends to be a bit more verbose than handwritten Verilog RTL code, it’s not off by much and it’s easy to see a 10x reduction here. In a paper published at DVCon 2012, a Cynthesizer user claimed a nearly 40x reduction in code. Now that is productivity improvement!

SystemC and HLS provide a myriad of benefits to the designers in the form of better productivity, better quality of results (QoR), and true design reuse through technology-independent design. What had been less clear are the substantial benefits in verification as well.

From high-level models developed much faster to high-speed verification, high-level synthesis really is about delivering a better methodology. It allows designers and verification engineers to spend time on real hardware design problems, not on mundane tasks required by the 20+ year old Verilog RTL methodology.

Follow me on Twitter at @BrettCline!





(Compared to TLM)

TLM Behavior



PIN Behavior



Verilog RTL



Cycle-Accurate RTL*