Forte CynCity

Russ Henke, a contributing editor at EDACafe, recently profiled Forte. We’re repurposing it here in its entirety because we think it’s an accurate depiction of where we’ve come from and what we’ve accomplished.

We hope you like it as much as we do. Please send your comments.

A Profile of Forte Design Systems

Let’s start with a picture of a building that’s likely to appear familiar to a lot of readers – the front of the New York City Public Library.

Did you know that the two marble lions prominently visible in front of the famous library are named “Patience” and “Fortitude?” We shall see how these words might also describe many of the people of Forte Design Systems, and perhaps similarly named statues should be placed in front of Forte’s headquarters at 100 Century Center Court in San Jose, CA.

The tale of this high-level synthesis company starts with the successful 2001 merger of two companies, CynApps and Chronology. Executives of the newly formed company wisely chose a descriptive name for the combined company, since “forte” means “good at” or “strength” though patience and fortitude, and the people of Forte have both in abundance.

Forte’s long-time vice president of marketing and sales Brett Cline said the following: “Forte’s been around for many years now and is the major driver of a whole new market segment. I consider us to be a definer of the high-level synthesis market. And, we’re good at it.”

The Forte Corporate Culture and its Founder
Let’s pause here and define from 10,000 feet the term “high-level synthesis software.” From all accounts, it enables electronics hardware engineers to work at a higher level of design abstraction.

Any story about Forte must start with Dr. John Sanguinetti, the EDA luminary noted for launching Chronologic in the 1990s and developing VCS, the Verilog Compiled Simulator, which is still in widespread use today.

After Chronologic was acquired by Viewlogic in 1994, he started looking for his next adventure. (As an aside, Viewlogic was itself acquired by Synopsys in 1997). Since Dr. Sanguinetti’s expertise was performance analysis and design verification, he understood that there were two basic problem areas in EDA –– logic verification and logic synthesis. He already had tackled logic verification; a closer look at logic synthesis seemed in order. For more than a decade, he had known that a change in abstraction levels from gates to RTL (Register Transfer Level –> see ”Acronyms” at conclusion of article) would improve design and verification efficiency, and that such a change might be enabled by logic synthesis.

A true entrepreneur in every sense of the word, John is Forte’s CTO today. He is also a 2011 ACM Fellow for contributions to hardware simulation. He serves as a role model and mentor for many entrepreneurs and engineers and has been quoted as saying: “In a technical field like EDA, understanding the problem, and understanding the technology, are prerequisites.”

Since John’s name is synonymous with the word entrepreneur, let’s find out how that came to pass. “I was caught up in startup fever from my first year in the Valley (1982). Ardent was my first real startup (1986), but it was a big-time operation –– I was #24. After that, I knew I wanted to start something, but it took a while to figure out what.” That something was Chronologic.

John has been and continues as an active angel investor in the EDA industry, helping drive EDA technology and businesses forward. He has put “seed” funding into many EDA companies that have had successful exits, including Ambit, Magma, Moscape, CoDesign, Surefire, Hier Design, Innologic and, most recently, Nextop. John has been or is actively involved in more than 20 other ventures as an angel investor, mostly in EDA and many still going.

Becoming an angel investor started innocently enough. “I was introduced to Rajeev Madhavan right after selling Chronologic to Viewlogic. Rajeev was trying to start Ambit, and I was interested right away.”

“I spent lots of time with Rajeev trying to pitch Ambit to interested VC’s. I not only made money on the investment, but gained a good friend, and felt like I had made a contribution to a worthwhile venture.”

John said he had no investment formula when he got started and referred to his early choices as “haphazard.” Many entrepreneurs approached him after his success with Chronologic and he found it hard to say no. After five or six years and a string of failures of promising ideas and technology in divergent fields, John restricted himself to EDA. “So far, none of my non-EDA investments had a positive return. All of my successes have been EDA.”

Influence on Forte
John’s technical vision, business acumen and hard-earned experience are strong parts of the corporate culture at Forte Design Systems.

Telecommuting has long been another hallmark of Forte’s corporate culture, something that’s far more common today with other companies than it was in 2001. Forte may be headquartered in San Jose, but it also has offices throughout the United States, including Pittsburgh PA, and Redmond WA, and international offices in England, Japan and Korea.

As Brett Cline, who works from Boston, pointed out, “It’s a small world. We may be in different states or on different continents, but we make use of all the available collaboration tools.” And it seems to be working.

Carving Out the High-Level Synthesis Market
In 1998, John Sanguinetti and two other engineers founded CynApps to create a higher level design environment, along with a synthesis product that would produce RTL code from higher level designs. A tool challenge and one not easily solved, and it took a long, long time, but Forte finally did it.

In this achievement we realize that this is where patience and fortitude paid off. Forte succeeded where other companies haven’t, by exhibiting dogged determination, winning over design teams one at a time, while the industry as a whole struggled to define the market category.

Long-time EDACafe readers might well recall the names of other companies with behavioral synthesis that morphed into architectural synthesis, ESL and algorithmic synthesis. None of the names stuck and their tools eventually failed. But Forte stayed on course with high-level synthesis, a term now widely adopted by the EDA industry, as the production-quality tools themselves go mainstream.

Success has finally come to Forte. John gives loads of credit to investors who believed in Forte and didn’t give up. In particular, Sam Lee, managing director at Infinity Capital, has been an investor since December 1999 and holds a board seat. Likewise, another EDA luminary Lucio Lanza of Lanza TechVentures participated in Forte’s Series A funding way back in November 1998 and has served continuously as chairman of the Forte board. “Stalwart” is the word John uses to describe both.

As an aside, investors in Forte’s first round of funding reads like a Silicon Valley Who’s Who: Andy Bechtolsheim, who was that series’ largest investor; Gordon Bell; Steve Blank; Paul Huang; and Jon Rubinstein.

Meet Sean Dart of Forte
Sean Dart is Forte’s CEO and is highly technical, an unusual combination in today’s business climate, but vital to an emerging EDA company. Sean grew up in a small town 400 miles north of Sydney, Australia, and moved to Sydney to study computer science at New South Wales University.

His decision to study computers was a curious one, considering Sean had never seen a computer. The decision came after talking to career counselors. He was a good student in all subjects but preferred scientific studies. The advice he received was that computing was the up and coming field. This appealed to Sean because he could combine his interest in math with the practical, giving him an opportunity to merge the intellectual with a job. And, he loved it.

Today, everybody has a personal computer, so it’s difficult to imagine the days of computer centers. [Maybe for Nanette, but not for others, such as your Contributing Editor]. Sean said that he and his colleagues used hand-marked cards, not even key punched cards. He mused that even later, the 30 VAX terminals from the computer lab at his college had one-thousandth the capabilities of an iPhone.

Sean’s first job out of college was working for STC (Standards Telephones & Cables) in Australia designing embedded programming for PBX systems. After two years, he was designing operating systems for small business computers and then moved on to Olivetti. He was subsequently transferred to Colorado to work with AT&T to customize telecommunications equipment for the Australian market. Once that project was abandoned, Sean and his American wife moved to Switzerland where he worked for a company that second-sourced ASIC designs. His role was to manage the network and develop tools and utilities to support the design services team. The company needed utilities, especially for verification, to help retarget designs.

After a fashion, the company decided it was making more money in the tools area and became an ESDA company, Sean’s introduction into EDA and a forerunner to high-level synthesis. The company, Speed Electronics, was sold in 1997 to Mentor Graphics.

After 10 years in Switzerland, the Dart family, that now included two children, relocated to Silicon Valley in pre-Internet 1997 but quickly discovered that the SF Bay Area was an expensive place to raise a family. After looking around the EDA companies in the Seattle and Boston areas, he liked what he saw at Chronology in Redmond, Wash., less than 20 miles from Seattle.

So in 1997, after only five months in Silicon Valley, he and his family moved to a town 15 miles east of Redmond. “It’s a great place to live,” he noted.

It’s at this point that we need to hear more from Brett Cline, who truly has his finger on the pulse of the high-level synthesis market and someone who has been a major contributor to Forte’s success. Brett may be a bit more informal than the consummate executive of old, but one is not fooled by the informality. Anyone who talks to him will pick up on his competitive streak. “Massively competitive,” he admitted, “I hate to lose and don’t accept losses that well. I push myself to do things better and I try to encourage others to exceed as well.” He admires winners, but firmly believes that it’s important to be a team player as well, something that’s apparently important as well to the 35 or so Forte employees.

You may have also heard that Brett is one marketing executive willing to dress in costume, as the situation calls for it. In 2003, he donned a hockey goalie uniform to present a DVCon paper titled, “Why You or Your Replacement will Use SystemC for System Design,” claiming he needed the padding for his defense in front of a room of skeptical RTL designers.

In 2005, Brett dressed in a chicken suit at DAC after losing a bet to John Cooley, editor of ESNUG and DeepChip. They agreed to a “Gentlemen’s Bet” over whether SystemC adoption would be more than 50% in the results of the DeepChip Verification Census. Brett said it would, John Cooley said it wouldn’t. John Cooley ruled that day, “but he was counting the votes,” laughed Brett. “It would be interesting to see if he is willing to make that bet again now.”

© 2012 Forte Design Systems/Brett Cline

© 2012 Forte Design Systems / Brett Cline

Brett is a friendly New Englander who grew up in Manchester, CT. He moved to Boston to attend Northeastern University and worked at GE as a co-op student. EDA has a few Northeastern grads, but younger readers may not know that Northeastern is renowned for its five-year co-op program where students get real-world experience by working in companies before graduating (Other schools of course offer co-op university programs, such as the University of Cincinnati where the Contributing Editor obtained his engineering degrees).

After graduating, Cadence in Massachusetts came calling because Brett’s background included both hardware and software. Brett was put to work on a waveform project, then VHDL simulation graphical tools and was tasked to work with the SimVision team. He enjoyed working with the sales and FAEs, and eventually moved into technical marketing for many of the same products he had spent time building.

SimTech recruited him in 1997 to be the East Coast application engineer, before SimTech was acquired by Summit Design that same year. In 1998, he ran marketing for the ex-SimTech products, then picked up corporate communications responsibilities as well.

It was in November 1999 that Brett called a friend at CynApps about joining. He knew the legend of Dr. John Sanguinetti from late nights at Cadence working with the Verilog-XL and NC-Sim teams to compete with VCS and Brett was eager to meet Dr. Sanguinetti.

Brett liked much of the CynApps story, especially the verification piece, but he remained a bit skeptical about behavioral synthesis, a still unproven technology. He wasn’t certain the electronics industry was ready for behavioral synthesis, but he became more and more excited about CynApps’ entire product portfolio, including a simulation library that could be marketed as an open source product with C++ simulation, services and debug and analysis tools that captured his imagination. He signed on and then CynApps acquired DASYS in January 2000, which further cemented the focus on behavioral synthesis.

Concluding remarks about John Sanguinetti
The first thing one learns about John Sanguinetti when talking with him, is his modesty. The second is his candor.

When asked what influenced him to study computer science, John said, “After my freshman year of college, I had a summer job in the Navy Department in Washington, D.C. where I wrote output reports in Fortran for a shipyard simulation program that was being developed. I learned Fortran from a self-study course that the government had. After that, I took as many programming courses as I could. This was 1967-70, when Computer Science was not much more than programming courses.”

While many of us associate John with Michigan and the University of Michigan, he’s originally from Silver Spring, MD, a suburb of Washington, D.C. “I went to college at University of Michigan for 11 years, so it’s fair to say I’m from Michigan, too.”

His fondness of the University of Michigan and Ann Arbor is strong. He met his wife in college and his daughter Anne was born in Michigan. “I still go back there to play in the alumni Marching Band at homecoming,” noted John. A fine trombone player since he was a teenager, he has also performed with the Peninsula Symphony for 25 years.

We talked as he was getting ready to leave on a vacation at the Maryland home he owns, a home that has been in his family for many years. It sits on the beach of the Chesapeake Bay, giving him ample opportunity to sail his Sunfish sailboat off the beach or take the wooden kayak he and his wife built several years ago.

Yes, a wooden kayak. John recalled finding a company that sells kits for building wooden boats. Over the course of two summers, two weeks at a time, they built a kayak now housed at Chesapeake Bay. He said, with characteristic modesty, that the experience was like any other woodworking project, which meant following directions. It was straightforward, though he recalled lots of sanding. And definitely a bit of patience and fortitude.

Merging Chronology and CynApps
The 2001 merger of CynApps and Chronology created an interesting dilemma and one that was debated all the way to the board room. The question was how to make Forte Design Systems both a verification company and a synthesis company. Chronology was making money as a verification provider, but was not doing as well as Verisity (now part of Cadence).

CynApps was making a little money in the synthesis area, though not enough to pay all the bills; however, it was able to secure funding to grow the company. The decision was made to continue to focus on high-level synthesis and to utilize the plethora of verification tools to build a high-level synthesis environment with verification at its core.

And in that same year, Sony, Ricoh and Fujitsu became high-level synthesis customers of the newly combined Forte and the push was on.

Moving to a high-level synthesis business model was practical. Cynthesizer, Forte’s high-level synthesis software, was gaining traction, though Brett Cline said that the first few years of the merger were killers as Forte honed down at least five products into essentially just one with add-on capabilities. (Chronology’s TimingDesigner was still around in a separate division and ultimately sold to EMA Design Automation in 2007.)

Asia adopted a high-level synthesis methodology ahead of other world regions, willingly making a huge investment in a methodology shift. John, Sean and Brett all credit this turning point to the large number of consumer electronics companies. The high-level synthesis trend started in Japan because consumer device designs were a natural fit for this kind of software. High-level synthesis can implement image-manipulation algorithms, for example, into hardware. Japanese hardware engineers saw high-level synthesis as a way to stay ahead of the design curve from challengers in Korea and China. Moving up the abstraction level and adopting SystemC was a way to leapfrog ahead.

Brett acknowledged a few key and savvy individuals who led this methodology shift, many of whom are still in the business.

At this point in our interview, Brett opened up a spreadsheet and noted that Japan accounted for 99% of 2004 HLS revenue. Over time, it’s become about half of Forte’s revenue and still remains a large and important region.  United States, Korea and Japan, in particular, are design centers where Cynthesizer is in use for all kinds of applications. The USA is Forte’s fastest growing region, designing everything from custom processors to wired and wireless communication devices.

As we’ve seen in this profile, acquisitions have been good for Forte and it did another in 2009. It acquired Arithmatica to complement its product offerings with a portfolio of IP and datapath synthesis technology that has been integrated directly into Forte’s Cynthesizer product.

Today, Cynthesizer is chosen primarily by design teams that want to reduce time-to-market pressures by designing at a higher level of abstraction and who require substantial improvements in circuit size and power. In many cases, teams create designs that would be impossible using RTL with their given resources.

The long-term benefit is generally not well understood. The value of SystemC-based IP and the ease at which it can be retargeted and reused is at the beginning of a project, are some things Verilog RTL has never achieved.

A Long Trek for Forte
“It’s been a long trek, in terms of finding the right set of customers who need a flexible format for IP reuse for the future,” said CEO Sean Dart. “Getting a product to that point was much harder than we expected. In 2000-2001, we never expected it to be this difficult. People shrug their shoulders and say, what’s so hard about a translator with clock cycles, far under-estimating what’s involved. The high-level synthesis tool needs to be able to handle different kinds of design styles, implementation methods and coding styles. It must be able to work with all of the downstream tools and libraries. It’s hundreds of things. Everybody underestimates the project.”

Many designers still hand code RTL for most of their designs, even now. Sean noted there’s a bit of inertia in the designer world, and Brett agreed. After all, any new change in the design flow can create more problems. For a designer, it introduces something new –– risk. They need to write in another language at another level of abstraction and change from what has been comfortable for them. “For a company like Forte, we need to prove we can make people successful and show a flexible format for reusing IP where a designer can get great results,” remarked Sean.

And, it finally happened with Cynthesizer. “We created a groundswell of support,” Sean stated, with Brett nodding his head in agreement. “Designers came to understand the utility. Otherwise, their product will miss the time-to-market window. IP development is so much shorter. Once people have the experience, then a second experience, that’s when the groundswell happened.”

He continued: “IP must be compatible and it should be automatically implementable. It’s a key selling point for us. There are reasons to buy the first time and a reason for change. Design teams don’t go into high-level synthesis for IP that will give them two or three times performance. However, as process geometries get smaller, fully timed RTL IP may not be reusable. That’s where high-level synthesis can make a difference.”

At this point, Sean became even more animated and noted: “High-level synthesis offers a way for designs to be retargetable for the next level and an optimal solution for technology, speed and longevity of the design. A key selling point for Cynthesizer is that the IP can be used on another project with almost zero effort.” Forte estimates that while the productivity gain on first development of an HLS-based IP may be 5-10X, reusing that IP block next time around yields over 25X.

“Design teams are experiencing that reuse benefit,” he concluded.

The Career Opportunity
A small company like Forte can offer loads of opportunity, as Sean and Brett found.

Sean’s moved into the CEO position in 2006 and yet is completely comfortable talking with engineering teams and understands their technical challenges. He can see their point of view and feel the pain of their daily lives.

Meeting customers, setting product directions was something Sean did as vice president of engineering. He was involved in many high-level meetings and traveled to Asia quite often. When he moved into the role of CEO, he learned more about the financial side of the business and working with the board and investors. Since assuming the CEO role, he sold a division (Chronology’s Timing Designer in 2007) and acquired a company (Arithmatica in 2009).

“I’ve had three different jobs at Forte and watched about 30 competitors come and go,” affirmed Brett. He started out in marketing at CynApps and was sidetracked in 2005 to work in an operations role for Forte. His task was to set up a post-sales support organization to make sure that Forte serviced its customers to ensure their success. That meant an explicit focus in post-sales support rather than an implicit one. “I’ve always tried to dive into whatever needed to be done and deliver to the best of my ability and, at the time, this was extremely important,” he reported. “Small companies must work closely with every customer to make sure each design project is a success.”

With that mission accomplished, Brett went back to marketing and took over sales in 2006. “We have grown each year since 2006 and we are proud of it,” he said. He also takes pride in having done a lot of things to merge new companies into Forte.

At this point, John Sanguinetti interjected: “It’s gotten a lot easier than it was before. I take a step back and see the market coming around to understand the need for high-level synthesis.” From there, he described a more mature product and a codified sales process that helps identify and better qualify opportunities, something Brett’s done over the past four years.

Sean concurred. Forte’s doing well and, from his perspective, keeping the momentum going is all important. His goal and one shared by Brett and John is to keep the team executing. “Our charter should be to create relationships with customers to get paid fairly for our products. The real trick is to deliver enough value and to be paid fairly for what we do.”

The EDA Industry
As the interview came to a close, Sean was asked for his perspective on EDA. He paused for a moment and answered: “Often the goals of the large (EDA) companies are different from those of the small (EDA) companies. Disrupting the status quo isn’t such a bad thing,” he added and believes that the need for continued innovation comes from small companies. “EDA is a small industry, but an important one. What would happen if everyone in EDA quit to build web pages? It would stop the world economy. We do have an important place in the ecosystem and should be recognized. We need to foster small EDA companies.”

John Sanguinetti, of course, agreed and had one final comment about Forte: “Patience and fortitude really do characterize Forte. We’ve kept at it and appreciate our success.”

So ends our current profile of Forte Design Systems. If personalities are the foundation of a successful company, Forte has them in spades. Forte’s people clearly exhibit the qualities from the names of the two lions in front of the New York Public Library: Patience and Fortitude!

Note: Forte has been the sponsor of a live bagpipers’ performance at DAC since 2001. EDACafe’s Peggy Aycinena captured this year’s performance. Her video is posted on her blog, “49DAC Unplugged:

http://www10.edacafe.com/blogs/whatwouldjoedo/2012/06/12/49dac-unplugged-images-from-san-francisco/

Acronyms:
ACM: Association for Computing Machinery
CEO: Chief Executive Officer
CTO: Chief Technical Officer
DAC: Design Automation Conference
EDA: Electronic Design Automation
ESDA: Electronic Systems Design Automation
ESL: Electronic System Level
GE: General Electric
nm: Nanometer
I/O: Input/Output
IP: Intellectual Property
RTL: Register Transfer Level
SoC: System on Chip
STC: Standards Telephones & Cables
VAX: Virtual Address eXtension, an early mainframe computer from Digital Equipment Corporation (DEC)
VCs: Venture Capitalists
VCS: Verilog Compiled Simulator

Forte Coverage:

EDN: “Sage words of advice from Forte Design Systems founder John Sanguinetti” by Brian Bailey

EDN: “Time to rethink EDA flows and tool infrastructure” by Brian Bailey

EDACafe’s What Would Joe Do: Forte: “Anchor Tenant in the ESL Mall” by Peggy Aycinena

EETimes: “2012 will be the year of power, again” by Brett Cline

EETimes’ EDA DesignLine: “Control dominated design” by Mike Meredith

EETimes’ EDA DesignLine: “Gearing Up for DAC – Above RTL” by Brian Bailey

Electronic Design: “Implement Abstraction By Encapsulation In SystemC” by Mike Meredith and John Sanguinetti

GABEonEDA: “Bagpipers a DAC Tradition” by Brett Cline

In the opening entry of this series, we introduced modular interfaces and talked about their importance in high-level synthesis (HLS). We touched on the ways that other HLS tools force you to create interfaces–with limiting approaches like ANSI C or off-the-shelf IP–and contrasted that against the strengths of our Cynthesizer tool. By designing with Cynthesizer using SystemC, we showed examples of how the verification, standardization and customization of interfaces is all made easier.

The second part of our series on modular interfaces deals with external memories. It’s unavoidable when you’re designing at an abstract level–at some point you’re going to need a memory. High level algorithms, by nature, make extensive use of loops that operate on arrayed datatypes. Not all HLS tools handle external memories well.  With some you have to schedule the memory interface by hand!  There are several different ways that Cynthesizer can implement those arrays for you, but it is when they become external memories that Cynthesizer’s modularity really shines.

Arrays In HLS
Let’s say you have an array in your design, maybe something like this:

sc_uint<16> mem[16];
…
for ( int i = 0; i < 16; i++)
{
    acc = acc + coeff * mem[i];
}

What can you do with it? Well, in Cynthesizer there are three things you can do. You can:

• Flatten it
  • Using a directive or command-line switch, Cynthesizer will flatten the array into individual registers. This is helpful if you want a short latency—your architecture will have access to all array locations in the fewest possible cycles.
• Make it an internal memory
  • Using Cynthesizer’s Memory Model Editor, you can create a memory model that Cynthesizer will allocate to store your array. This is good if you have a few extra cycles to spare and don’t want the added muxing of a flattened architecture.
• Make it an external memory
  • Using the same memory model, you can instruct Cynthesizer to implement the memory externally.  Cynthesizer will synthesize an interface to this memory for you. You will not have to worry about controlling the address, data or enable ports.

It is the ease of making a memory external (and the lack of changes required to your SystemC source code) that we will get into now.

Going External
So you want your array to be an external memory? First thing you need to do is build it. To do that you can invoke the Memory Model Editor in the Cynthesizer Workbench GUI. Here’s what it looks like:

[Click to enlarge]

There’s actually not that much you have to do here. We set “Word Size:” and “Number of Words:” both to 16 to match our array’s size and indices. The “Latency:” is 1 by default, and the “Setup time:” and “Output Delay:” should be a nonzero time value based on the data from your technology library. And since this memory will be external, the “Area:” is 0.

By default this will be a single-port memory. If you want something different you can click the “Ports” tab, where you can increase the number of ports, edit the names of the address and data lines, specify any enable lines or masking, associate each port with a clock or reset, and configure the ports as read-only, write-only or both.

But the real power for us is in the “Internal memories” and “External memories” boxes where you can specify chaining or registering of the memory I/O. That’s right, the SystemC memory model we create will be usable as either an internal or external memory.

So once we’ve generated the memory model (I called it “mem_part”), how do we use it? All you have to do is turn your array declaration into a memory port instantiation. Previously we had this:

sc_uint<16> mem[16];

now we have this:

mem_part::port<ioConfig, sc_uint<16> >  mem;

port<> is a templated class in the generated SystemC memory model that represents an external port connection. Its arguments are the I/O configuration, which can be defined for TLM or pin-level simulation, and its datatype. The memory model will also have to be connected to clock and reset but there are high-level functions available to do that.  Why, you ask, do we have to do all this?  Chances are you chose an external memory because it needs to be shared with other modules.  The classes like port<> make it possible to accurately simulate intermodule communication through a shared memory at the behavioral level.  With other tools that use ANSI C or don’t have customizable interfaces, you have to wait till you have RTL to verify anything like this.

What do you have to do to the source code? Well, nothing:

for ( int i = 0; i < 16; i++)
{
    acc = acc + coeff * mem[i];
}

The array access looks exactly the same as before. Cynthesizer knows to associate your array access with an external memory port, and it schedules the interface automatically based on your latency constraints.  The external memory has become a truly modular interface, and it was all created for you. If you generate RTL for this design you will see the synthesized interface in the port list:

module dut(clock, RSTN, inp_busy, inp_vld, inp_data, outp_busy,
           outp_vld, outp_data, mem_WE0, mem_DINw, mem_DOUTw,
           mem_Aw, mem_REQ0);
  input clock;
  input RSTN;
  …
  input [15:0] mem_DOUTw;
  output mem_WE0;
  reg mem_WE0;
  output [15:0] mem_DINw;
  output [3:0] mem_Aw;
  reg [3:0] mem_Aw;
  output mem_REQ0;
  …

Next time, we’ll take a look at the techniques used to build custom modular interfaces using Cynthesizer’s Interface Editor.